The present invention relates to a method of forming a mask blank and a mask used for the lithography for manufacturing semiconductor devices and, more particularly, to a structure of a mask blank for fabricating a mask which transcribes a mask pattern onto a wafer using charged particle beams such as electron beams and ion beams and a method for forming a mask blank and a mask used for the charged particle beam exposure.
With miniaturization and increase in integration of semiconductor elements in semiconductor integrated circuits, an electron-beam projection lithography for transcribing a predetermined configuration onto a wafer using charged particle beams, especially using electron beams, was developed instead of the conventional photolithography using light. Recently, the development of EPL (Electron-beam Projection Lithography) method achieving higher throughput has advanced. As an electron-beam projection lithography, there is a method in which a prescribed mask pattern is divided into a plurality of sections, stencil masks formed with opening patterns each having a predetermined size and a predetermined arrangement are prepared, and electron beams are incident on the sections so that electron beams thus formed by the opening patterns are transcribed onto a wafer as a subject substrate on some reduced scale. There has been developed a system for forming a device pattern by combining prescribed patterns separately formed on the mask onto the subject substrate (for example, see Patent Document 1).
The stencil mask used for the aforementioned electron-beam projection lithography comprises a silicon membrane defining through-holes for transmitting electron beams in which a pattern region is divided and reinforced by a supporting grillage, referred to as “strut”, from the back, thereby reducing the distortion of the pattern region and improving the accuracy of position of the pattern region. The typical method of forming a stencil mask will be described with reference to FIGS. 5(a)-5(e).
As shown in FIG. 5(a), as a substrate for a stencil mask, SOI (Silicon On Insulator) substrate 51 is conventionally used which has a silicon oxide film between silicon and silicon. An SOI substrate 51 is reliable because SOI substrates have been practically employed as semiconductor circuit substrates for LSI and a silicon membrane 52 as an upper layer for fabrication of pattern possesses higher reliability in quality concerning zero defects and thickness uniformity. The SOI substrate 51 has a structure in which two silicon crystal substrates are bonded with a silicon oxide film 53 intervened therebetween. A supporting silicon layer 54 to be a strut has a thickness of several hundreds μm, the silicon membrane 52 for forming a mask pattern has a thickness of several μm, and the silicon oxide film 53 which functions as an etching stop layer during fabrication of the mask blank and fabrication of the mask has a thickness of about 1 μm.
Masking material such as Cr for silicon etching is spattered onto the silicon membrane 52 for the fabrication of the mask pattern of the SOI substrate 51, thereby forming a hard mask layer 55 (FIG. 5(b)).
Then, a protective coat for etching is formed by photoresist or the like in order to form an opening in the back of the substrate corresponding to an exposed region and silicon is partially removed by way of dry-etching from the back of the substrate up to the silicon oxide film 53 functioning as the etching stop layer so as to form the opening 56. After that, the resist is removed, thereby forming a mask blank 58 (FIG. 5(c)).
An electron-beam resist is coated on the front-side hard mask layer 55. A predetermined pattern is formed by exposure of an electron-beam writer and is developed. The hard mask layer 55 is removed at exposed portions by way of etching so as to form a patterned hard mask layer 59. After the electron-beam resist is removed, the silicon membrane is removed at the exposed portions by way of dry-etching so as to form electron-beam through-holes 60. In this manner, a mask pattern 61 is formed (FIG. 5(d)).
Then, the patterned hard mask layer 59 is removed and the silicon oxide film as the etching stop layer 53 is removed at the opening 56, thereby forming a stencil mask 63 (FIG. 5(e)).
In order to prevent the deformation of the mask pattern layer 61 due to the compression stress of the residual silicon oxide film 62, boron or the like may be previously doped into the surface silicon membrane 52 of the SOI substrate 51 so as to impart tensile stress.
According to the conventional forming method as mentioned above, however, the silicon membrane is deformed due to the compression stress about 300 MPa of the silicon oxide film 53 interposed because the silicon layer supporting from the back is removed in the step of FIG. 5(c) where the back-side silicon is partially removed by way of dry-etching to form the opening 56. As a result, distortion of about 20 μm is generated as shown in FIG. 6. As the mask is formed using the blank 58 with this distortion, a problem is caused that the position of the desired pattern such as LSI may be greatly shifted.
As an alternative method of the aforementioned forming method, there is a forming method without using SOI substrate as mask substrate (for example, see non patent document 1). This method includes forming an etching stop layer on silicon crystal plane by way of sputtering and further forming a silicon membrane on the etching stop layer by way of sputtering so as to prepare a mask substrate.
However, the silicon membrane which is required to have highest quality characteristics in the mask and mask blank is in amorphous state because the silicon membrane is formed by using sputtering technique in the method without using SOI substrate. Therefore unlike the single crystal silicon of the SOI substrate, the silicon membrane is not dense. If abnormal particles of silicon are generated, defects are produced. Accordingly, it is difficult to form a thin silicon layer without defects and having uniform thickness. Thus, there is a problem that it is hard to obtain a high quality mask using a mask blank prepared by this forming method.
[Patent Document 1]
Japanese Patent No. 2829942
[Non-patent Document 1]
Abstracts of The 46th International Conference on Electron, Ion and Photon Beam Technology and Nanofabrication, p401, “Fabrication of complete 8″ stencil mask for electron projection lithography”.